1. Field of the Invention
The present invention relates to a solid state image sensing device, and manufacturing and driving methods thereof, particularly, relates to a solid state image sensing device provided with an amplifying element having a ring shaped gate electrode in each pixel and manufacturing and driving methods thereof.
2. Description of the Related Art
Solid state image sensing devices are divided broadly into two types: the one is a charge coupled device (CCD) and the other is a complimentary metal oxide semiconductor (CMOS) image sensor. The CCD out of the two types of solid state image sensing devices transfers an electric charge, which is obtained through photoelectric conversion process by a photo diode, outside a pixel. The electric charge is converted into a voltage signal and amplified, and then outputted outside the CCD chip.
On the other hand, in the case of a CMOS image sensor, the CCD image sensor converts an electric charge, which is obtained through the photoelectric conversion process by a photo diode, into an electrical signal such as a voltage signal and a current signal in a pixel, and then the electrical signal is outputted outside the pixel. Almost all CMOS image sensors are provided with a transistor for amplifying in each pixel. Consequently, a CMOS image sensor is often provided with more than three transistors in one pixel. A lot of space of one pixel is devoted to these transistors, so that a CMOS image sensor is said to be disadvantageous to miniaturization in comparison with a CCD.
In this connection, a type of image sensor having only one or two transistors in one pixel has been developed. A transistor provided in such a type of image sensor is characterized by having a ring shaped gate electrode. Generally, diffusion in the middle of the ring of the ring shaped gate electrode functions as a source of the transistor. However, the diffusion is isolated from other diffusion by the ring shaped gate electrode, so that configuration of the transistor enables to be simplified. In this regard, such a type of image sensor should be categorized as one type of CMOS image sensor as far as the image sensor is provided with a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) for amplifying in each pixel.
The most typical example of such an image sensor is a solid state image sensing device called the CMD (Charge Modulation Device), which was disclosed in the Japanese publication of unexamined patent applications No. 60-206063/1985.
FIG. 32 is a cross sectional view of the solid state image sensing device called the CMD according to the first prior art. In FIG. 32, the conventional solid state image sensing device is composed of a p−-type substrate 501, an n−-type epitaxial layer 502 that is grown with constituting a channel area on the p-type substrate 501, an n+-type circular source diffusion layer 503 that is formed by adding n-type impurities into the n−-type epitaxial layer 502, an n+-type drain diffusion layer 504 that is concentrically formed with completely surrounding the n+-type circular source diffusion layer 503, a source electrode 505, and a drain electrode 506, wherein the source electrode 505 and the drain electrode 506 is made from aluminum and jointed to the n+-type circular source diffusion layer 503 and the n+-type drain diffusion layer 504 respectively.
Further, a p-type gate area 507 is formed on the surface of the n−-type epitaxial layer 502 through a process such as the ion implantation method so as to cove over the n+-type source diffusion layer 503 and the n+-type drain diffusion layer 504.
Furthermore, a concentric insulative gate is formed by providing a gate electrode 509 made from a transparent conductive material on the surface of the n−-type epitaxial layer 503 between the n+-type circular source diffusion layer 503 and the n+-type drain diffusion layer 504 with sandwiching a gate insulative film 508 so as to completely surround the n+-type circular source diffusion layer 503.
In the CMD having the above-mentioned configuration, a depletion layer is formed by applying certain voltage to the gate electrode 509, and conducted to be a light receiving section, that is, a so-called photo gate type light receiving element, which is simple in configuration such that one transistor combines a light receiving element with an amplifying element. Electric charges pooled right under the gate electrode 509 make threshold voltage of the transistor change by the substrate effect, make an output voltage of the source change, and result in an electrical signal. A hole is discharged to the substrate when a high voltage is applied to the source electrode 505 and the gate electrode 509 after the electrical signal is read out.
However, the photo gate type light receiving element mentioned above is weak in sensitivity in comparison with an buried photo diode that is commonly used in a CCD because light is absorbed while the light passes through the gate electrode 509.
Further, there exists a problem such that noise easily occurs in an interfacial area of the gate insulative film 508 although the gate area 107 as a p-well directly contacts with the interfacial area of the gate insulative film 508.
Furthermore, there exists another problem such that generated electric charges are evenly distributed over the gate electrode 509 by this configuration, and resulting in degrading efficiency of converting an electric charge into voltage.
In order to improve the problems, the Japanese publication of unexamined patent applications No. 11-195778/1999 disclosed a solid state image sensing device. The solid state image sensing device is in the configuration that is provided with not only a light receiving diode and an insulative gate type field effect transistor (FET) sharing a well area but also a concentrated buried layer (carrier pocket), which is provided adjacent to a source diffusion area in the well area under a channel area of the FET.
FIG. 33 is a cross sectional view of the solid state image sensing device according to the second prior art disclosed in the Japanese publication of unexamined patent applications No. 11-195778/1999. In FIG. 33, the solid state image sensing device is a ring shaped MOSFET, which is provided with an n-well 612 that is formed on the surface of a p+-type substrate 611, an buried p-well 613 that is formed in the n-well 612, a ring shaped gate electrode 614 that is formed on the buried p-well 613, an n+-type drain diffusion layer 615 that is also formed on the buried p-well 613 so as to surround the outer circumferential area of the gate electrode 614, and an n+-type source diffusion layer 616 that is formed in the middle of the ring shaped gate electrode 614.
In this configuration, the buried p-well 613, which is provided under the n+-type drain diffusion layer 615 of the ring shaped MOSFET, is conducted to be an buried photo diode. Then, a p+ area (hereinafter referred to as carrier pocket) 617 is formed in an area adjacent to the n+-type source diffusion layer 616 of the MOSFET as a highly concentrated buried layer of which concentration of p-type impurity is increased. By this configuration, since an electric potential of the carrier pocket 617 is the lowest in the buried p-well 613, a hole generated by incident light in the buried photo diode provided under the n+-type drain diffusion layer 615 moves inside the buried p-well 613, and is concentrated in the carrier pocket 617. Consequently, voltage of an area adjacent to the source increases and threshold of the MOSFET decreases, so that change of the threshold results in an electrical signal. Holes concentrated in the carrier pocket 617 are discharged by applying a high voltage across a wiring 618 for the source electrode 616 and another wiring 619 for the gate electrode 614 after the electrical signal is read out.
As mentioned above, in the conventional solid state image sensing device, all electric charges generated by incident light move through a substrate as the buried p-well 613 without passing over the surface of the substrate in which noise easily occurs. Therefore, the conventional solid state image sensing device is characterized by low noise.
Further, generated electric charges are concentrated in the neighborhood of the source diffusion layer 616, so that the conventional solid state image sensing device is also characterized in that efficiency of converting an electric charge into voltage increases more.
The solid state image sensing devices disclosed in the Japanese publication of unexamined patent applications Nos. 60-206063/1985 and 11-195778/1999 adopt a so-called electric rolling shutter imaging system. The electric rolling shutter imaging system is such an imaging system that imaging time is shifted at each line or by each pixel. Such a rolling shutter imaging system causes a problem such that a picture being imaged is distorted when imaging a moving object or panning a camera. Consequently, a so-called frame shutter or global shutter imaging system in which time information is aligned at whole pixels is desirable for the imaging system. In the case of a CCD, electric charges generated by photo diodes in whole pixels are simultaneously transferred to a transfer path of the CCD, so that the frame shutter is accomplished.
The Japanese publication of unexamined patent applications No. 10-41493/1998 has disclosed the solid state image sensing device, which was provided with the ring shaped gate electrode and realized the frame shutter.
FIG. 34 is a cross sectional view of the solid state image sensing device according to the third prior art disclosed in the Japanese publication of unexamined patent applications No. 11-195778/1999. In FIG. 34, the solid state image sensing device is provided with a p-type substrate 721, an n-type semiconductor area (hereinafter referred to as n-well) 722 that is formed on the p-type substrate 721, a p-type semiconductor area 723 that is formed on a part of the n-well 722 constituting a unit pixel, and an n+-type semiconductor area 724 in highly concentrated form that is formed on the p-type semiconductor area 723, wherein these n+-type semiconductor area 724, p-type semiconductor area 723 and n-well 722 constitute a light receiving section that is called a photo diode sensor. The p-type semiconductor area 723 is equivalent to an area in where a signal charge generated by the photoelectric conversion is accumulated.
Further, a p-type semiconductor area 725 is formed on a part of the n-well 722 that constitutes a unit pixel, and then a ring shaped gate electrode 727 is formed above the surface of the p-type semiconductor area 725 with sandwiching a gate insulative film 726.
Furthermore, an n+-type source area 728 and an n+-type drain area 729 is formed in the p-type semiconductor area 725, wherein the n+-type source area 728 is formed in an area disposed right under the center portion of the ring shaped gate electrode 727, and wherein the n+-type drain area 729 is formed in another area corresponding to the outer peripheral area of the ring shaped gate electrode 727. Then the source electrode 731 is formed above the n+-type source area 728 with sandwiching the gate insulative film 726. Consequently, a CMOS transistor for reading out signals is formed, wherein the p-type semiconductor area 725 provided right under the gate electrode 727 functions as a signal charge accumulating section.
In addition thereto, a transfer gate electrode 730 is formed on the gate insulative film 726 in an area, which is allocated between the light receiving section and the CMOS transistor, above the n+-type semiconductor area 724.
As mentioned above, the conventional solid state image sensing device according to the third prior art shown in FIG. 34 is added with one transfer gate electrode 730, which is allocated in the area between the buried photo diode as the light receiving section and the ring shaped gate electrode 727. The conventional solid state image sensing device transfers signal charges, which are obtained through the photoelectric conversion in the light receiving section and accumulated in the p-type semiconductor area 723, to the p-type semiconductor area 725 disposed under the ring shaped gate electrode 727 by means of the transfer gate electrode 730 simultaneously with respect to whole pixels. Consequently, the frame shutter is accomplished. The conventional solid state image sensing device shown in FIG. 34 is identical to the conventional CMD according to the second prior art shown in FIG. 33 as far as the not buried p-type semiconductor area 725 spreads over whole area disposed under the ring shaped gate electrode 727.
The conventional solid state image sensing devices having the conventional ring shaped gate electrode resulted in following problems.
In the case of the conventional solid state image sensing device according to the second prior art disclosed in the Japanese publication of unexamined patent applications No. 11-195778/1999, as shown in FIG. 33, the carrier pocket 617 is constituted by providing a p+-area in the buried p-well 613, so that the p+-area is inevitably led to be excessively high in concentration. Consequently, voltage for resetting an electric charge in the carrier pocket 617 becomes higher. High voltage as high as 7 to 8 volts, for example, is essential. Since high voltage is essential to be applied as mentioned above, power consumption increases, and resulting in a problem such that a booster circuit is necessary to be provided.
In order to decrease the resetting voltage, it has only to reduce p+ concentration of the carrier pocket 617. However, it is impossible, in principle, to reduce the p+ concentration of the carrier pocket 617 lower than concentration of the buried p-well 613.
Further, an effect of concentrating electric charges is degraded otherwise the p+ concentration of the carrier pocket 617 is sufficiently higher than that of the p-well 613. Consequently, it should be understood that there exists restriction for designating a range of p+ concentration of the carrier pocket 617.
On the other hand, for the purpose of realizing the frame shutter, it just has to provide one transfer gate electrode as the same manner as the conventional solid state image sensing device according to the third prior art disclosed in the Japanese publication of unexamined patent applications No. 10-41493/1998 shown in FIG. 34. However, the configuration of the transistor having the ring shaped gate electrode is identical to that of the conventional CMD according to the second prior art disclosed in the Japanese publication of unexamined patent applications No. 11-195778/1999, and the p-well is provided in whole area disposed under the ring shaped gate electrode, so that concentrating electric charges in the source area is disabled. Consequently, there exists a problem such that efficiency of converting an electric charge into voltage is degraded.